1. Field
The present description relates to the field of regulating clocked gates in integrated circuits and, in particular, to regulating the clock so that it is supplied to a clocked gate only when needed.
2. Related Art
Flip-flop circuits are widely used in complex electronic systems such as memory, counters, timers, buffers and in a wide range of other applications. A flip-flop circuit, also referred to as a latch or a bistable multivibrator, in a simple form, is an electronic circuit that receives an input (D, T or J) and, in response, produces a stable output voltage (Q) at one of two different output voltages. Since the output voltage is stable and changes only in response to the input, flip-flops have become a common component for one bit of memory. More complex flip-flops may be controlled by two or more control signals, and a gate or clock signal (CLK). The output may include the stable single voltage (Q) and also its complement (QN), i.e. the other voltage.
A simple flip-flop has two cross-coupled inverting elements. These are typically transistors, but may also be implemented as NAND or NOR logic gates. A clocked or strobed flip-flop may also include a gating mechanism, for the gate, clock, or strobe input. A clocked flip-flop only responds to the input value when the gate, clock or strobe signal permits it. This is usually when the gate signal transitions from high to low or from low to high. The flip-flop, whether gated or not, when it receives its input either maintains or changes its output signal. In more complex designs, a master-slave architecture may be used in which two basic flip-flops are combined to reduce the sensitivity to spikes and noise between short clock transitions. Other designs may also include clear (R, reset) or set (S) inputs which may be used to change the current output independent of the clock.
Integrated circuits are usually designed using existing components that are combined together to create the circuit. This avoids the expense and delay of designing standard components each time. For example, to design an ASIC (Application Specific Integrated Circuit), a controller, a DSP (Digital Signal Processor), or other integrated circuit, flows are typically used that synthesize gate level netlists from a high level language such as Verilog HDL (Hardware Description Language). The gate level netlists are usually provided as part of a gate level library provided by a library vendor. The flip-flops in a typical gate level library are normally designed for robust operation in a wide variety of applications and clock scenarios. For some specific applications, the general designs may not be satisfactory.
One specific application for flip-flop circuits is for very low-power circuits. The general flip-flop circuit designs are not normally optimized for low power consumption. Power consumption is normally traded for reliability and speed of operation. Another specific application for flip-flop circuits is in circuits with imprecise clock or gate timing. Standard ASIC flip-flop circuits are designed to fit a clocking methodology that is responsive only to single positive edge clocking. This means that when the voltage of the in put clock signal begins to rise from it low state to its high state, the gate is triggered, activating the flip-flop circuit.
This methodology has the benefit of being very well understood and having extensive support in common computer design tools. However, single positive edge clocking introduces implementation risk around the management of hold times. For reliable operation of a group of such flip-flops, the delivery of the clock to every flip-flop in the design has to be controlled to within a few hundred picoseconds (ps) of clock skew. This may be difficult to ensure with low power, with finer line integrated circuit fabrication processes (e.g. 130 nm and below), and with the introduction of signal integrity issues that are difficult to accurately model.